Welcome to the ITBHU Chronicle, December 2011 Edition Interviews Section.
Interviews
Dr. P. R. Chidambaram (Metallurgy 1986), Director of Technology, Qualcomm, California
@ Dec 17, 2011
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We are pleased to publish the interview with Dr. P. R. Chidambaram, who has contributed to the research and development of SiGe (Silicon-Germanium) transistors and championed the use of these transistors in cell phone chips such as the upcoming Qualcomm Snapdragon®® S4 MSM8960 integrated dual core CPU/LTE modem.

P. R. Chidambaram has a B. Tech in Metallurgy from the Institute of Technology, Banaras Hindu University (1986), a Masters in Material Science from Virginia Poly Technic Institute and State University (1988, Virginia Tech) and a PhD from Colorado School of Mines (1992, CSM) in material science.

After graduating, he taught at CSM as a research assistant professor for a couple of years before joining Texas Instruments. As a Director of Technology, Chidi (as P. R. Chidambaram is known) currently manages both the 20LP and the coming 20SOC programs at Qualcomm.

At Texas Instruments, Chidi held various R&D positions on semiconductor technology development. He has 37 issued patents from the USPTO (United States Patent and Trademark Office) and a few more that are in review. His key innovation on the straining transistors by growing embedded SiGe close to the gate of the transistor is now widely used in the industry. The paper (P. R. Chidambaram et al. VLSI Tech digest pp. 46, 2004) describing this innovation is referenced over 100 times.

In 2007 he joined Qualcomm to lead the 28LP technology and implement the SiGe process at Qualcomm. This technology is the key enabler for the upcoming S4 Snapdragon® processor code named MSM 8960 which is the world’s first single chip with the dual core Snapdragon® CPU and LTE modem. In 2012, this chip will bring lap-top features to the mobile phone by booting Windows and Android operating systems. As a Director of Technology, Chidi now manages both the 20LP and the coming 20SOC programs at Qualcomm.

Yogesh K. Upadhyaya from Chronicle talks with Mr. Chidambaram to find out more about his research background.

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(Dr. P R Chidambaram)

Dr.  P. R. Chidambaram can be contacted at: pchidi@gmail.com

Q-1: Welcome Sir. It is nice to know that you were involved in the pioneer research in the SiGe Technology. Please explain the research work.

 By the year 2000, the semiconductor industry realized progress in semiconductor scaling. Scaling, also known as Moore’s law, says that every two years you will get the same chip performance at half the cost. Scaling is limited for some key material science issues. Plain electrical engineering approach to miniaturizing CMOS (Complementary metal–oxide–semiconductor) transistors were over and we needed disruptive Materials Science approaches to enhance performance. Across the industry we were all in a competitive race to stress the electrons and holes to improve the mobility. With epitaxial SiGe, we squeeze a larger size atom into the trench dug on either side of the transistor channel and in the process develop a compressive strain in the channel that improves the hole mobility and PMOS drive current by >35%. Intel was first to bring this to production with the embedded-SiGe. However, their implementation was inefficient since it was spaced 40nm away from the gate. My team’s research work at Texas Instruments is credited with innovating the optimal SiGe implementation closer to the gate. This allows for a lower SiGe volume and less dislocation defects. We also showed with high resolution TEM and convergent beam analysis the magnitude to the strain induced in the channel by the embedded SiGe layer. 

Q-2: Please describe your current research work as Director of Technology at Qualcomm.

Qualcomm is the leader in the semiconductor chips used in cell phones - both Radios and CPU. These cell phone chips that Qualcomm builds are like Intel CPUs for laptop or desktop. I direct the new process technology introduction team that works with the leading foundry. Every two years we switch to the new technology to reduce chip area, cost, and power. We also improve the speed of processors. Rapid new technology introduction over the next few years will bring computer and game console class performances to cell phones and tablets.

Q-3: What is the current trend in the research in semiconductor industry?

Semiconductor engineering is a rapidly evolving field with 30 year strong history of innovation. More computer class features such as 1080P video, online-mobile gaming will be available on cell phone and tablets based on transistor we build in the upcoming years. Managing the behavior of few atoms in the quantum confined transistor channel is critical to increasing the battery life of your cell phone. When you make them smaller, these transistors also switch faster and enable the voice calls to migrate to video calls. Although many in this field are still electrical engineers, new innovations tend to be multi-disciplinary.

Q-4: How did you get interested in research field?

I have always been interested in research. I even wrote a technical article for Benares Metallurgist. There are very few Industries that are actively involved in research. The semiconductor industry is one of the few areas where companies generate future profit and margin based on research and development. Over the past 30 thirty years many first order effects have been exploited to scale down the transistors. Shear demand for user experience will keep this industry going for many more years to come. However, this will require clever and careful engineering leveraging physics from many related fields. Therefore, there is good scope for innovative engineers that have multi-disciplinary training in the semiconductor industry

Q-5: Please tell us about yourself.

I was born in Chennai (1965) and spent most of my formative years there. Learning faster than your competition and willingness to change the way you do things are the keys to doing well in my industry. In fact, they are the key to succeeding in any area. I have been a long time student of Gandhi. Although, I may not agree with all this philosophy, I am inspired by his spirit to experiment with everything and his wiliness to execute based on the learning. There are many who talk about good philosophy, but he is the one who lived by it. Currently I live in San Diego with my wife Anitha and son Bhairav (14)

Q-6: Please tell us about your college days.

I have relied on people over profession most of my career. At BHU I could have joined the more popular mechanical engineering dept. I choose Metallurgy because it had more recognized faculty. It has paid off well in my career. Undergraduate years are where you lay foundations of your technical knowledge and good teachers make all the difference. At IITs, we have a rare opportunity to be around exceptional people fellow students in particular. Although, I remained in school 11 years after IT BHU, I have never been able to be around such high caliber talent. I have had few good classmates at Virginia or Colorado but on average BHU was the best.    

Thank you Sir.

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Education of Dr. P R Chidambaram:

*B Tech. (1986) in Metallurgical Engineering, from Institute of technology, Banaras Hindu University, Varanasi, India.

*MS (1988) in Material Science, from Virginia Tech, Blacksburg, Virginia, USA

*PhD (1992) in Material Science, from Colorado School of Mines, Golden, Colorado, USA

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Dr. P. R. Chidambaram in Research news

Leading IEEE journal editors invited Chidi to review the strained silicon technology that is published in IEEE Transactions on electron devices (P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, "Fundamentals of Silicon Material Properties for Successful Exploitation of Strain Engineering in Modern CMOS Manufacturing," Electron Devices, IEEE Transactions on, vol. 53, pp. 944, 2006); also, he has presented various invited talks, trade journal articles on this subject.

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Qualcomm Shies Away from High-k at 28nm

http://semimd.com/blog/2011/02/07/qualcomm-shies-away-from-high-k-at-28nm/

(February 2007 article)

by David Lammers

Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy – which because of Qualcomm’s size will have a major impact on the foundry business — at the 2010 International Electron Devices Meeting (IEDM) held in San Francisco.

Jim Clifford, senior vice president of operations, said the decision to stick with a poly/SiON process was related to timing and cost issues. “High-k inherently requires more mask layers, and there are defect density issues that make it a little more challenging,” Clifford said in an interview at IEDM.

Qualcomm is not closing the door on HKMG. “There is a class of products where you need it,” Clifford said, including some chips made for tablet computers and the “extremely high-end” smart phones. Qualcomm may use the HKMG processes at the later stages of the 28nm node for those products, which require roughly 2 GHz and higher frequencies. But for most of its high-volume smart phone chipsets, Qualcomm will stick with the less expensive poly/SiON process.

In a luncheon keynote speech at IEDM, Clifford emphasized that while Qualcomm is hungry for smaller and faster transistors, he is growing increasingly concerned about the costs involved with EUV lithography and other technologies required to stay on a Moore’s Law cadence. “I’m all about costs,” Clifford said.

In an IEDM paper on its 28nm technology, Qualcomm technology director P.R. Chidambaram said a high-k process without significant strain on the channel does not offer an advantage over a poly-SiON process with strain techniques. “A HKMG process with strong strain engineering offers a substantial speed gain but with a higher cost, making it more suitable for smartpad/tablets and extreme high-end smartphones. A poly/SiON process enables a quicker time to market with less process risk, and historical defect density reduction,” he said.

Most of the Qualcomm smart phone chipsets, based on the company’s Snapdragon® processor core, run at 1 Ghz or less, and can be served by going to dual-core designs. Geoff Yeap, senior director of technology, said the Snapdragon®-based chips sold by Qualcomm “have huge volumes,” adding that the high-k processes at the major foundries “are not ready yet.”

Yeap said Qualcomm will move a limited number of products to the HKMG foundry processes at a later point. While HKMG transistors generate higher drive currents from the increased inversion charge, the switching capacitance increases due to the need to charge up the gate to gain the higher drive current. Linear drive current (Idlin) is more important than saturation current (Idsat) for Qualcomm, he added.

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Qualcomm limits leakage with several techniques

While HKMG helps out with power leakage at the gate, it doesn’t do much to improve power lost at the substrate and in the source-drain areas. Qualcomm has been able to contain power consumption by using well biasing, as well as circuit techniques such as power and clock gating. A specially designed power gating switch was described by Chidambaram, who cited it as an example of the close cooperation between Qualcomm technologists and engineers at an unnamed foundry partner.

The 28 nm node offers major advantages to Qualcomm, which combines RF, digital processing, and analog functionality on its SoCs. Moving from 45 to 28 nm design rules supports a 2.4 times increase in gate density, a 55% reduction in power and a 30% gain in frequency, said Chidambaram.

At IEDM, some technologists expressed surprise at Qualcomm’s decision to stick with a largely SiON process, citing better electrical control of the channel as well as improved variability from HKMG technology. Overall, the industry was in a holding pattern, unable to scale the effective oxide thickness after the 90 nm node until high-k came along, resulting in a reliance on strain techniques to boost speeds.

GlobalFoundries has a technology roadmap which relies on a gate-first HKMG for all of its low power and high performance offerings. Qualcomm’s decision to stick with a largely poly/SiON process raises the question of whether GlobalFoundries will switch gears and offer a poly SiON process at the 28nm node, in part to support Qualcomm, the largest foundry customer worldwide.

Clifford was asked if Qualcomm would use GlobalFoundries as a foundry supplier at the 28 nm node, but he said he preferred not comment, saying that choice of foundries is still under discussion.

A GlobalFoundries spokesman said all of the foundry’s 28nm offerings on its “public roadmap” are based on gate-first HKMG. “However, we are offering a 28 nm Poly/SiON technology at the specific request of certain customers with product applications that do not require the performance and leakage benefits provided by our HKMG technology,” he said. GlobalFoundries will not be enabling a design ecosystem around 28 nm Poly/SiON.

He added that the HKMG ramp is “still on track and we are seeing significant customer traction. We expect HKMG to be the volume leader at 28nm in both low power mobile applications as well as high performance wired applications.” Multiple customer designs have been silicon-validated, and test chips are in prototyping at the company Fab 1, in Dresden, Germany, and are on the way to early risk production.

GlobalFoundries and TSMC have engaged in a marketing battle over the benefits of their competing approaches to HKMG: gate first for GlobalFoundries and gate last for TSMC. GlobalFoundries claims that its gate first HKMG process has a 10-15% cost advantage over the TSMC gate last process.

Yeap said that at the 22/20nm generation, Qualcomm plans to use HKMG for nearly all of its products.

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IBM adds HOT sauce to carrier mobility recipe

http://www.eetimes.com/electronics-news/4049295/IBM-adds-HOT-sauce-to-carrier-mobility-recipe

(June 2004 news article)

Excerpts:

“David Lammers

6/21/2004 9:00 AM EDT

HONOLULU — With most of the chip industry embracing strained silicon to increase carrier mobility, researchers at IBM Corp. — which itself is pursuing strained silicon — and several other companies are investigating hybrid-orientation silicon as yet another path to the same objective.

Mindful of the looming inability to shrink silicon dioxide thickness further as leakage currents hit practical limits, researchers are enhancing electron and hole mobility in the conducting channel to enable continued improvements in device speed. IBM came to the 2004 Symposium on VLSI Technology here last week with three progress reports on its hybrid-orientation technology (HOT), which combines a 110-oriented crystal lattice for the PMOS transistors with a 100 lattice for NMOS.

HOT builds on IBM's work with silicon-on-insulator technology, and IBM claims the technique can complement strained silicon.”……..

 “One debate at the symposium centered on whether the HOT approach could be used in addition to the process-induced strain approach. Intel Corp.'s strain approach, for example, would not work with a hybrid-orientation technology. But the IBM researchers said HOT and process-induced strain could be complementary.

On its own, process-induced strain is proving surprisingly effective at increasing mobility, particularly for the holes that serve as carriers in the PMOS devices. The strain reduces the holes' effective mass as well as the carrier scattering rates.

Process-induced strain is often referred to as local strain, to differentiate it from the more costly, "global" approach, which starts with a SiGe layer across the entire wafer. Process strain was once assumed to be far less effective than the global approach in boosting performance, but now technologists are realizing that while the level of strain may be lower with the local approach, the mobility enhancement is as good as or better, said Thomas Skotnicki, a research manager at STMicroelectronics in Crolles, France.

At last week's symposium, technology managers from Intel and Texas Instruments Inc. detailed their respective companies' approaches to strained silicon. Both deposit silicon germanium in the recessed source and drain regions of the PMOS device. That puts enough of a strain on the silicon lattice in the nearby channel to increase hole mobility sharply.

P.R. Chidambaram, a member of the technical staff at Texas Instruments, said TI's approach "brings the SiGe right next to the gate, which squeezes the channel in the transverse direction, as well as putting the silicon under tensile strain. For holes, both help, and we are seeing dramatic numbers as a result."

For TI's test silicon, hole mobility rose 70 percent, with a 35 percent increase in drive current for the PMOS devices.”

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Additional Links:

* Qualcomm, San Diego, California, USA.

http://www.qualcomm.com/

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From its beginnings in 1985, Qualcomm has grown from seven individuals meeting in a den to a world-leading provider of wireless technology and services. Qualcomm is a global company, a firm with many facets, with each business division changing the way we live and work through its own unique contributions. But no matter what each Qualcomm business does, all are united by a single, driving passion: to continue to deliver the world’s most innovative wireless solutions.

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* Virginia Tech

http://www.vt.edu/

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Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA.

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Dedicated to its motto, Ut Prosim (That I May Serve), Virginia Tech takes a hands-on, engaging approach to education, preparing scholars to be leaders in their fields and communities. As the commonwealth’s most comprehensive university and its leading research institution, Virginia Tech offers 215 undergraduate and graduate degree programs to more than 30,000 students and manages a research portfolio of nearly $400 million. The university fulfills its land-grant mission of transforming knowledge to practice through technological leadership and by fueling economic growth and job creation locally, regionally, and across Virginia.

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* Colorado School of Mines, Golden, Colorado, USA

http://www.mines.edu/

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About Colorado School of Mines

Engineering the Way

Colorado School of Mines is a public research university devoted to engineering and applied science. It has the highest admissions standards of any public university in Colorado and among the highest of any public university in the U.S.

Mines has distinguished itself by developing a curriculum and research program geared towards responsible stewardship of the earth and its resources. In addition to strong education and research programs in traditional fields of science and engineering, Mines is one of a very few institutions in the world having broad expertise in resource exploration, extraction, production and utilization. As such, Mines occupies a unique position among the world's institutions of higher education.

Since its founding in 1874, the translation of the school's mission into educational programs has been influenced by the needs of society. Those needs are now focused more clearly than ever before. The world faces a crisis in balancing resource availability with environmental protection and Mines and its programs are central to the solution.

Mines offers all the advantages of a world-class research institution with a size that allows for personal attention. 

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